ASIC Digital Design Engineer , Proto 

Team Overview

Proto is accelerating the world's transition to an open economy with products that increase access and independence for everyone. We're building hardware and software that will help decentralize bitcoin mining and enable new and innovative use cases for bitcoin mining. We're developing our products in the open - you can read more at mining.build. Come build the future of money with us!

We believe everyone should be able to participate and thrive in the economy. We believe bitcoin plays an essential role in the future of payments and the world’s economy. We believe that the status quo of bitcoin mining does not serve the mission of the bitcoin ecosystem. So we’re building a bitcoin mining rig powered by Block designed custom ASICs. With our mining rig, we can address many issues such as the concentration of hardware supply in certain countries and incompatibility with clean energy sources.

As an ASIC Digital Design Engineer, you will work closely with other digital designers and physical designers to develop the next generation of mining ASIC. In particular, the challenges of chip/block level implementation, timing, integration, and verification are critical parts of this role. 

We are a distributed team across the U.S. and Canada, and are hiring for a single remote position. 

Main responsibilities will include:

• Chip/block level design and verification 
• IP integration 
• Synthesis
• Debugging RTL and GLS failures

You Have:

• BS in Electrical Engineering or Computer Engineering with at least 5 years of digital design and verification industry experience
• Proven number of years of industry RTL (Verilog / System Verilog) ASIC design experience through implementations targeting leading edge ASIC technologies
• Skilled in simulation and debugging with functional verification tools from Synopsys including Gate-level simulations
• Proficient with scripting languages such as Python, Perl, TCL, Makefile.
• Understanding of the SPI/UART communication protocol 
• Understanding of the IP integration and interactions within an ASIC
• Strong analytical skills and attention to detail
• Excellent written and communication skills
• Must be a self-starter and able to independently drive tasks to completion
• Demonstrates the ability to debug issues and quickly identify viable solutions

Even better if you have experience with:

• MS in Electrical Engineering or Computer Engineering 
• STA timing signoff experience using Synopsys PrimeTime

• Some Knowledge of physical PnR, custom cells and library etc.
• Background working with Synopsys EDA tools (e.g. Design Compiler/Fusion Compiler, PrimeTime, Formality, Spyglass, Verdi, VCS etc)
• Some Knowledge of design and verification on FPGA 

We’re working to build a more inclusive economy where our customers have equal access to opportunity, and we strive to live by these same values in building our workplace. Block is an equal opportunity employer evaluating all employees and job applicants without regard to identity or any legally protected class. We will consider qualified applicants with arrest or conviction records for employment in accordance with state and local laws and “fair chance” ordinances.

We believe in being fair, and are committed to an inclusive interview experience, including providing reasonable accommodations to disabled applicants throughout the recruitment process. We encourage applicants to share any needed accommodations with their recruiter, who will treat these requests as confidentially as possible. Want to learn more about what we’re doing to build a workplace that is fair and square? Check out our I+D page.